Encoder
Input
Reads encoder inputs of the Q8 data
acquisition system.
Library
qctools
Description
The Encoder Input Module for the Q8 series
of I/O cards provides a mechanism for reading the encoder count of
any encoder input on an installed Q8 I/O card. The block can provide
a scalar or vector output.
Parameters and Dialog Box
Board Number
The board number of the I/O card. If
there is only one Q8 board in your system, then the board number
should be zero. The second Q8 board in your system is board number 1,
etc.
Channel(s) to Use
The channel
numbers corresponding to each output. For example, if there are 3
outputs, then the entry [4,2,0] assigns output 1 to encoder input 4,
output 2 to encoder input 2 and output 3 to encoder input 0. The
channel numbers may range from 0 to 7, since there are 8 encoder
channels on the Q8 I/O boards.
This block reads all selected channels
simultaneously if both even and odd channels are specified.
For example, to read channels 0, 1 and 2 at exactly the same time,
specify channels 0-3 as the Channels to Use. Encoder channels read
from separate Encoder Input blocks will not be read simultaneously.
All eight channels can be sampled simultaneously.
Initial Value(s)
Initial value for the encoder count of
each channel specified in the Channel(s) to Use parameter. If
Channel(s) to Use is [3,2,0] as above, then an entry of [0,1000,0]
for the Initial Value(s) will set encoder channels 3 and 0 to 0, and
encoder channel 2 to 1000 when the simulation is initiated. A scalar
value applies to all channels.
Sample Time
A sample time must be specified for
all discrete blocks. The default value extracts the sample time from
the RTW Options dialog, under Solver/Fixed step size. A numeric value
rather than 'auto' should be specified in this dialog field for this
default to make sense.
Quadrature
Indicates the type of quadrature
encoding to use for all selected channels. The Q8 card provides 1X,
2X or 4X quadrature. The 4X quadrature mode is the default since it
provides the highest encoder resolution, yielding four times the
encoder resolution. For example, a 1024 count encoder will produce
4096 counts per revolution in 4X quadrature mode. In quadrature mode
the A and B inputs are digitally filtered and decoded for the up/down
counter.
If non-quadrature mode is selected,
then the A and B inputs of the encoder DIN connectors are treated as
CNT and DIR inputs respectively. A pulse on the CNT input causes the
encoder counter to either increment or decrement according to the DIR
input. DIR = 1 selects upward counting and DIR = 0 selects downward
counting.
Count Mode
The counting mode for all selected
channels. The modes are as follows:
Normal.
The 24-bit encoder counter wraps when it overflows or underflows ie,
it cycles from 16777215 (0xffffff ) to 0 when counting upward.
Range
Limit. In range limit count mode, an upper and a lower
limit is set, mimicking limit switches in the mechanical counterpart.
The upper limit is set by the Initial Value parameter and the lower
limit is set to 0. The counter freezes when at the Initial Value when
counting up and at zero when counting down. At either of these
limits, the counting is resumed only when the count direction is
reversed.
Non-Recycle.
In non-recycle count mode, the counter is disabled whenever a count
overflow or underflow takes place. The end of cycle is marked by the
generation of a Carry (in Up Count) or a Borrow (in Down Count). The
counter is re-enabled when a reset or load operation is performed on
the counter. The counter can be loaded in response to an index pulse
or via software.
Modulo-N.
In modulo-N count
mode, a count boundary is set between 0 and the Initial Value. When
counting up, at the Initial Value, the counter is reset to 0 and the
up count is continued from that point. When counting down, at zero,
the CNTR is loaded with the content of Initial Value and the down
count is continued from that point. The modulo-N is truly
bidirectional in that the divide-by-N output frequency is generated
in both the up and down direction of counting for the same N and does
not require the complement of N in the UP instance. In frequency
divider applications, the modulo-N output frequency can be obtained
at either the Compare (FLG1) or the Borrow (FLG2) output. The
modulo-N output frequency is fN = (fi
/ (N+ 1) ) where fi = input
count frequency and N=Initial Value.
Interrupt Flags
The encoders have two flag outputs.
Each flag may be used as an interrupt source for asynchronous
interrupts (see the Encoder Interrupts block) or for polling (see the
Poll Encoder Interrupts block and Encoder Status block). This option
selects the meaning of those flags. The selected flags are used for
each selected channel. The flags are as follows:
CARRY.
When the 24-bit encoder counter overflows ie, cycles from 16777215
(0xffffff ) to 0 when counting upward, the CARRY flag goes low for
one cycle of the filter clock.
BORROW.
When the 24-bit encoder counter underflows ie, cycles from 0 to
16777215 (0xffffff ) when counting downward, the BORROW flag goes low
for one cycle of the filter clock.
CARRY/BORROW.
When the 24-bit encoder counter overflows or underflows ie, cycles
from 0 to 16777215 (0xffffff ) or vice versa, the CARRY/BORROW flag
goes low for one cycle of the filter clock.
COMPARE.
When the 24-bit encoder counter equals the Initial Value, the COMPARE
flag goes low for one cycle of the filter clock.
IDX.
Set to 1 when the index is valid. Otherwise set to 0. This flag is
meaningless if the Enable Index option is not checked.
E.
Set to 1 when excessive noise is present at the inputs.
UP/DOWN.
When the 24-bit encoder counter is counting upward, this flag is 1.
When it is counting downward, the flag is 0. If the counter is not
changing then the previous state is output.
Filter Clock Prescaling
In quadrature mode (1X, 2X or 4X), the
A and B encoder inputs are digitally filtered. The base filter clock
frequency is 16.7 MHz (60ns period). The prescaling divides this base
frequency. Hence, a filter clock prescaling value of 17 yields a
filter clock frequency of about 1 MHz. The
filter clock frequency must be at least eight times the maximum
frequency of the A and B inputs for proper operation.
Filter Clock Frequency
This parameter
cannot be modified, but is convenient because it displays the final
filter clock frequency after prescaling.
Binary-Coded-Decimal
When this option
is checked, the 24-bit encoder counter operates in binary-coded
decimal mode. Otherwise, it is a binary counter. This option should
generally never be checked but may be used in very specialized
applications.
Enable Index
When this option
is checked, the index pulse is enabled. Otherwise, index pulses are
ignored. When index pulses are disabled, the index input is treated
as high. Note that the IDX flag is meaningless when this option is
unchecked. Enable the index pulse if you wish to use the IDX flag
with one of the Encoder Interrupt, Poll Encoder Interrupt or Encoder
Status blocks.
Index Polarity
This option
determines whether an index pulse is recognized on the rising edge
("positive") or falling edge ("negative") of the
index pulse in one of the quadrature modes (1X, 2X or 4X). In
non-quadrature mode, this option is ignored and the index input is
treated as level-sensitive and active-low.
Reload Count on Index Pulse
When this option
is checked, a pulse on the encoder index input causes the encoder
counter to be reset to the Initial Value. This option applies to all
channels. For more flexibility with regards to the index pulse, refer
to the blocks in the Encoder Extras library. In non-quadrature mode,
a low-level at the encoder index input causes the encoder counter to
be reset to the Initial Value.
Simulation Input
When the Simulation Input box is
checked, the block will have an input port. During normal simulation
(as opposed to running real-time), the signal at this input will be
converted to a 24-bit encoder count and produced at the output. This
check box has no effect on the real-time code.
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